NROM fabrication method with a periphery portion
US5966603A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 11, 1997 |
| Grant date | Oct 12, 1999 |
| Priority date | — |
| Expiry date | Jun 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
Abstract
A method of fabricating a nitride read only memory (NROM) chip creates an oxide-nitride-oxide (ONO) layer on a substrate and etches the ONO layer within the memory portion of the chip into columns. Bit lines are implanted between columns after which bit line oxides are generated on top of the bit lines with the thickness of the bit line oxides being independent of the thickness of the bottom oxide. The thickness of a gate oxide layer in a periphery portion of the chip is also relatively independent of the thicknesses of the other oxides. Finally, rows of polysilicon or polysilicide are formed perpendicular to and on top of the bit line oxides and the ONO columns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.