Reduction of poly depletion in semiconductor integrated circuits
US5966605A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 7, 1997 |
| Grant date | Oct 12, 1999 |
| Priority date | — |
| Expiry date | Nov 7, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/268
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a transistor includes the steps of forming a gate structure (56) overlying a gate oxide layer (54), wherein the gate structure (56) and gate oxide layer (54) overlie a substrate (50), thereby separating the substrate (50) into a first region (90) and a second region (92) with a channel region therebetween. The method also includes doping the gate structure (56), the first region (90) and the second region (92) and annealing the doped gate structure (56) with a laser anneal, thereby driving the dopant through a substantial depth of the gate structure (56). Lastly, a source region (94) and a drain region (96) are formed in the first region (90) and the second region (92), respectively, wherein the dopant is further driven into the gate structure (56). Consequently, the dopant is driven substantially deeper in the gate structure (56) than in the shallow source region (94) and drain region (96) junctions to allow decoupling of poly depletion from the need for shallow junctions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.