Method of fabricating capacitor plate
US5966610A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1998 |
| Grant date | Oct 12, 1999 |
| Priority date | — |
| Expiry date | Jan 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
Abstract
A method of fabricating a capacitor plate constitutes first providing a substrate. Then, first insulating layer is formed over the substrate. Sequentially, a buffering layer and a second insulating layer, both of which constitute a stacked structure, are formed over the first insulating layer. Next, the stacked structure is patterned into an opening thereby exposing a portion of the first insulating layer therethrough. Subsequently, conducting spacers are formed on the sidewalls of the opening. The second insulating layer is thereafter removed, and simultaneously a portion of the first insulating layer not covered by the buffering layer and the conducting spacers are removed to form a contact window, thereby exposing a portion of the substrate therethrough. Then, a conducting layer is conformably deposited over the substrate, and thereafter etched away until a portion of the buffering layer is exposed. Finally, the exposed buffering layer is removed. The remaining conducting layer and the conducting spacers constitute the capacitor's bottom electrode plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.