Narrow data width DRAM with low latency page-hit operations
US5969997A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1997 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | Oct 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed Random Access Memory (RAM) array device includes several logical banks, each of which can be uniquely addressed. Each of these logical banks contains a unique memory array segment and associated page register, the latter serving as a temporary storage location during high-speed page hit operations. To reduce latency during an initial page hit, further array optimization is realized by segmenting each logical bank into two segments with one, smaller segment, comprising a faster random access memory (FRAM) for storing initial data in a data stream. A high speed page register connects the FRAM directly to a multiplexer/demultiplexer connected to the device I/O ports bypassing an internal bus protocol such that the initial data can be transferred between the FRAM and the I/O ports faster thereby improving page-hit latency. Hence, segmenting the logical banks to include only a small high speed segment results in a performance gain approaching what could be achieved by implementing the entire memory device with a high speed FRAM, but at much lower cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.