Patent · US Expired

Method of forming multilayer amorphous silicon antifuse

US5970372A · kind A · utility

33Cited by
12References
11Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 30, 1997
Grant dateOct 19, 1999
Priority date
Expiry dateDec 30, 2017

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/3011
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Antifuses are provided which include first and second conductive layers and an antifuse layer positioned between the first and second conductive layers. The antifuse layer includes at least one oxide layer positioned between two amorphous silicon layers. Interconnect structures and programmable logic devices are also provided which include the antifuses.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.