Device analysis for face down chip
US5972725A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1997 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Dec 11, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of precisely measuring electrical parameters in integrated circuits in a face down semiconductor device in which a portion of the semiconductor substrate is removed from the semiconductor device and an SEM microprobe is directed onto selected regions of the surface exposed by the removal of the semiconductor substrate. The microprobe is directed to selected regions of the exposed surface by a computer generated mapping system. One of the selected regions that the microprobe is directed to is a region of the exposed surface overlying a depletion region associated with a drain of a transistor in the semiconductor device. The voltage variation on the exposed surface caused by the expansion and shrinking of the depletion region is measured by the microprobe. Another region that the microprobe is directed to is a region of the exposed surface overlying an insulator and the microprobe detects the voltage of a conducting electrode under the insulator is measured via capacitive coupling. A third region that the microprobe is directed to is a region overlying a reverse-biased junction in the semiconductor device and a change in voltage of the reverse-biased junction is determined b…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.