Low supply voltage negative charge pump
US5973979A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 1996 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Dec 26, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/075
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.