Bit line biasing method to eliminate program disturbance in a non-volatile memory device and memory device employing the same
US5978267A · kind A · utility
30Cited by
9References
10Claims
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Key dates
| Filing date | Oct 20, 1998 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Oct 20, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.