Bias condition and X-decoder circuit of flash memory array
US5978277A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1998 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Sep 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
New bias conditions for flash memory cells and X-decoder circuits for providing the bias conditions. In an erasing operation, a positive high voltage is provided to the bulk and a negative high voltage is provided to the control gate for establishing a sufficient electric field to induce electron tunneling effect. In an operation for repairing a cell's threshold voltage, the biased voltages are reversed. A first X-decoder circuit structure is presented for supplying positive and negative high voltages to the memory cells for block erasing or repairing. The first X-decoder circuit structure has a plurality of X-decoder blocks each being constructed in a separated X-decoder well, and the memory cells are fabricated in a separate common array well. A second X-decoder circuit structure is presented to provide an appropriate bias condition for erasing or repairing a small sector of word lines. For the second X-decoder circuit structure, each memory block is fabricated in a separated array well. Separated X-decoder wells are constructed to provide voltages to the word lines of memory blocks. Every word line in a memory block has an X-decoder driver so that the word line can be erased or …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.