Method of fabricating DRAM capacitor

US5981334A · kind A · utility

Inventors

• Sun-Chieh Chien · Hsinchu, TW
• Jason Jenq · Pingtung City, TW
• C. C. Hsue · Hsinchu, TW

Key dates

• Filing date: Nov 6, 1997
• Grant date: Nov 9, 1999
• Expiry date: Nov 6, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/716

Abstract

A method for fabricating DRAM capacitor which includes forming a transistor having a source/drain regions and a gate electrode above a silicon substrate; then, forming sequentially a stack of layers including a first insulating layer, a second insulating layer, a third insulating layer and a hard mask layer over the transistor; subsequently, patterning and etching the hard mask layer. Thereafter, an oxide layer is formed over the hard mask layer, and then portions of the layers are etched to form a capacitor region over the oxide layer and a contact opening exposing a portion of the source/drain region. In the subsequent step, a conducting layer is formed over the oxide layer, the hard mask layer, the sidewalls of the contact opening and the exposed portion of the source/drain region. Next, a polishing method is used to remove the conducting layer above the oxide layer, and then the oxide layer is removed to form a lower electrode. A dielectric layer is then formed over the lower electrode, and finally an upper electrode layer is formed over the dielectric layer.