Method and semiconductor circuit for maintaining integrity of field threshold voltage requirements

US5981994A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• David Kuan-Yu Liu · Cupertino, US
• Jian Chen · San Jose, US
• Ming Sang Kwan · San Leandro, US

Key dates

• Filing date: Oct 30, 1995
• Grant date: Nov 9, 1999
• Expiry date: Oct 30, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A method for maintaining a high field threshold voltage in a plurality of transistors of reduced size in a periphery region of a Flash EPROM semiconductor circuit includes forming a first polysilicon layer as a floating poly in a predetermined number of transistors of the plurality of transistors in the periphery region, and forming a second polysilicon layer as a common gate line in the plurality of transistors, wherein the predetermined number of transistors prevent breakdown of the plurality of transistors below a predetermined field threshold voltage. In one aspect, the field oxide layer has a thickness of about 2500 angstroms. A plurality of transistors formed in a substrate of a periphery region of a Flash EPROM semiconductor circuit includes a first predetermined number of periphery transistors having a floating poly and a common gate line, and a second predetermined number of periphery transistors having the common gate line and adjacent the first predetermined number of transistors, the first predetermined number of transistors preventing breakdown of the second predetermined number of periphery transistors below a predetermined field threshold voltage.