Enhanced method of testing semiconductor devices having nonvolatile elements
US5982683A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1998 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Mar 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An enhanced method of testing semiconductor devices having nonvolatile elements by determining regions of the semiconductor having differing orders of probability that a defect will occur. The enhanced method of testing includes testing of regions from the highest probability to the lowest probability of having a defect. Nonvolatile memory elements in the region being tested are placed in a high impedance state, bypass circuits in the region being tested are activated to bypass the nonvolatile memory elements that control the state of elements in the region being tested and test vectors are applied to the elements that are controlled by the bypassed nonvolatile memory elements. This procedure is repeated for the next untested region having the highest probability of having a defect until all regions have been tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.