Semiconductor memory having redundancy circuit
US5983358A · kind A · utility
4Cited by
7References
15Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Sep 26, 1997 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Sep 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory having a redundancy circuit includes a judgment device for receiving outputs of first ROMs for storing a defective address therein and judging whether or not a defective memory cell and a spare memory cell to replace the defective memory cell belong to the same memory cell, and also includes a timing adjustment circuit for changing the timing of control signals applied to memory mat control circuits according to an output of the judgment device. When the defective and spare memory cells belong to the same memory mat, the timing of the control signals is made fast.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.