Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers
US5985771A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1998 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Apr 7, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02271
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of said at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions. In another aspect, the invention includes a method of reducing stress on semiconductive wafer, the semiconductive wafer having a pair of opposing surfaces and having more silicon nitride over one of the opposing surfaces than over the other of the opposing surfaces, the method comprising providing the silicon nitride over the one of the opposing surfaces to comprise a first portion, a second portion and a third portion, the first, second and third portions being elevationally displaced relative to one another, the second portion being between the first and third portions, the second portion having a greater stoichiometric amount of silicon than the first and third portions, the semiconductive wafer being subjected to less stress than …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.