Package stack via bottom leaded plastic (BLP) packaging
US5986209A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 1997 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Jul 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3426
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaged semiconductor device has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of inverted-J leads, short stub leads, vertically bent leads-in-grooves, or may be entirely eliminated. Lead connections are on the bottom package surface, over the top package surface, and/or on the sides and ends of the package, enabling vertical stacking of the devices and simultaneous/alternative coplanar horizontal connections to other semiconductor devices, circuit boards, etc. A mold assembly with a castellated inner surface forms a package with alternating grooves and columns for holding side and end electrical connection surfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.