Guard wall to reduce delamination effects within a semiconductor die
US5986315A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1993 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Aug 26, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a guard wall for a semiconductor die is described. A dielectric layer is deposited over a semiconductor substrate. The dielectric layer is patterned to form a guard wall opening extending through the dielectric layer. The guard wall opening lies adjacent to an electrically active region of the die. The guard wall opening has a pattern without any straight line segments greater than about 10 .mu.m long. A first layer is deposited over the substrate and etched to form a first layer sidewall spacer along a side of the guard wall opening. A second layer is deposited within the guard wall opening to form the guard wall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.