Test head structure for integrated circuit tester
US5986447A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 1998 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Mar 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2889
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test head for an integrated circuit-tester includes a horizontal base holding a circular motherboard. The motherboard distributes input test instructions to an array of carrier boards mounted thereon, the carrier boards being radially distributed about a central vertical axis of the motherboard. Each carrier board holds a set of daughterboards, and each daughterboard holds a set of node cards. The carrier boards and daughterboards include data paths for forwarding the test instructions from the motherboard to the node cards. Each node card contains circuits for transmitting test signals to and receiving response signals from a separate terminal of a device under test (DUT) in response to the test instructions forwarded thereto. Edges of the carrier boards extend downward through apertures in the base to contact pads on an interface board holding the DUT. The carrier boards and daughterboards provide conductive paths for the test and response signals extending between the node cards and pads on the DUT interface board. The interface board extends those conductive paths from the pads to terminals of the DUT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.