Method and apparatus for hiding data path equilibration time
US5986955A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1999 |
| Grant date | Nov 16, 1999 |
| Priority date | — |
| Expiry date | Jan 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hidden data path minimizes equilibration delays in coupling differential data through a complementary data path. The hidden data path may be used for both reading and writing to the memory cell array. The hidden data path includes two sets of complementary I/O lines coupled in parallel between the memory cell array and the DC sense amplifier, and are alternatively coupled between the memory cell array and the DC sense amplifier to receive and transmit data. The set of complementary I/O lines not coupled is equilibrated during this time in preparation for coupling to and transmitting subsequent differential data. The hidden data path may also include two sets of data read lines coupled in parallel between the DC sense amplifier and the output circuitry if used for reading data from the memory cell array. Similarly, a second set of data write lines may be coupled in parallel between the input circuitry and write driver circuit when used for writing data to the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.