David D. Siek
13Patents
8h-index
8Co-inventors
57Inventor score
Filing activity: Jul 16, 1996 → Jun 30, 2005
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6066870A | Single digit line with cell contact interconnect | Emerging Cross-Sectional Technologies | 128 | Expired |
| US5986955A | Method and apparatus for hiding data path equilibration time | Physics | 67 | Expired |
| US6735132B2 | 6F2 DRAM array with apparatus for stress testing an isolation gate and method | Electricity | 39 | Expired |
| US6496027B1 | System for testing integrated circuit devices | Physics | 32 | Expired |
| US6930503B2 | System for testing integrated circuit devices | Physics | 16 | Expired |
| US6590817B2 | 6F2 DRAM array with apparatus for stress testing an isolation gate and method | Electricity | 14 | Expired |
| US6756805B2 | System for testing integrated circuit devices | Physics | 11 | Expired |
| US6510533B1 | Method for detecting or repairing intercell defects in more than one array of a memory device | Physics | 10 | Expired |
| US5866928A | Single digit line with cell contact interconnect | Emerging Cross-Sectional Technologies | 7 | Expired |
| US6870750B2 | DRAM array and computer system | Electricity | 5 | Expired |
| US6167541A | Method for detecting or preparing intercell defects in more than one array of a memory device | Physics | 5 | Expired |
| US7180802B2 | Method of stress-testing an isolation gate in a dynamic random access memory | Electricity | 3 | Expired |
| US6999362B2 | Method of stress-testing an isolation gate in a dynamic random access memory | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.