Method of customizing integrated circuits by depositing two resist layers to selectively pattern layer interconnect material
US5989783A · kind A · utility
7Cited by
11References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 1998 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Mar 12, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T156/1983
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating custom integrated circuits includes the steps of 1) patterning a photoresist layer on an insulative layer with a standard via precision mask to define all possible vias, and 2) using a targeting energy beam to select the desired via locations on a second photoresist layer, which are then etched and interconnections made, for customization or repair of the integrated circuit. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.