2F-square memory cell for gigabit memory applications
US5990509A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 1997 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Jan 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, each having a channel formed between source and drain regions. Two transistors are formed per pillar. This is achieved by forming two gates per pillar formed on opposite pillar sidewalls which are along the bitline direction. This forms two wordlines or gates per pillar arranged in the wordline direction. The source regions are self-aligned and located below the pillars. The source regions of adjacent bit lines are isolated from each other without increasing the cell size. Two floating gates per pillar may be used for EEPROM or flash memory application. The isolated sources allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM applications, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively. When two capacitors or two …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.