Voltage biasing for magnetic ram with magnetic tunnel memory cells
US5991193A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1997 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Dec 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory array includes a substrate, a first plurality of electrically conductive traces formed on the substrate, a second plurality of electrically conductive traces formed on the substrate and overlapping the first plurality of traces at a plurality of intersection regions, and a plurality of memory cells formed on the substrate. Each memory cell is located at an intersection region between one of the first plurality of traces and one of the second plurality of traces and includes a bidirectionally conducting nonlinear resistance selection device and a magneto-resistive element electrically coupled in series with the selection device. The array is biased during a read operation by biasing a selected trace of a first plurality of electrically conductive traces at a first bias potential. All other traces of the first plurality of conductive traces are biased at a second bias potential. A selected trace of a second plurality of conductive traces is biased at a third bias potential. Lastly, all other traces of the second plurality of conductive traces are biased at the first bias potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.