Method for reducing program disturb during self-boosting in a NAND flash memory
US5991202A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1998 |
| Grant date | Nov 23, 1999 |
| Priority date | — |
| Expiry date | Sep 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory system is programmed with minimal program disturb and pass disturb during self-boosting without resorting to impurity implantation for bit line isolation, to p-well biasing or to bit line biasing techniques. A program voltage is applied to a selected word line in the form of a plurality of short pulses while synchronously applying a pulsed pass voltage to the unselected word lines until the selected cell is programmed. The duration of the pulses and the time between pulses are chosen to minimize the program disturb of unselected cells, especially unselected cells on the selected word line, without causing pass disturb of any cell in the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.