Method of making chip mountings and assemblies
US5994222A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 1997 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Apr 25, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bonding component for electrically connecting a semiconductor chip or wafer to a support substrate includes a dielectric layer having a central region, elongated slots defining the central region, and a peripheral region surrounding the slots. Metallic bonding pads are arranged on the central region, and leads extend from the bonding pads to the edge of the central region and extending partially across the elongated slots. The leads are detached from the peripheral region of the dielectric layer on the side of the slots opposite the central region. The leads are adapted to be deformed during bonding to a semiconductor chip or wafer. To form the bonding component, a dielectric layer is first provided having a central region, slots and a peripheral region. A metallic structure is also provided having bonding pads on the central region, and leads electrically connected to the bonding pads and to a plating bus disposed in the peripheral region. A resist is applied to the metallic structure in zones separating the leads, the metallic structure is plated in regions outside the zones with an etch resistant metal, the resist is removed and the leads are etched so as to form gaps in the m…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.