Simultaneous operation flash memory device with a flexible bank partition architecture
US5995415A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Sep 23, 1998 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Sep 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises a memory array 20 including a plurality of memory cells arranged in a plurality of columns and rows, a plurality of bit lines 28 and 30 each coupled to a respective column of the memory cells, each of the bit lines comprising first and second bit line segments separated by a gap designating a memory partition boundary between upper and lower memory banks, and an X-decoder 22 coupled to the respective rows of the memory cells to row decode the memory array in response to receiving upper and lower bank memory addresses. Two pre-decoders 24 and 26 are coupled to the X-decoder 22. Two Y-decoders 32 and 34 are coupled to the bit line segments to provide column decoding for the memory cells in the upper and lower memory banks, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.