Management of both renamed and architected registers in a superscalar computer system
US5996063A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1997 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Mar 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to the area of register renaming and allocation in superscalar computer systems. When a multitude of instructions in the instruction stream reads from or writes to a certain logical register, said logical register will have to be represented by a multitude of physical registers. Therefore, there have to exist several physical rename registers per logical register. The oldest one of said rename registers defines the architected state of the computer system, the in-order state. The invention provides a method for administration of the various register instances. Both the registers representing the in-order state and the various rename instances are kept in one common circular buffer. There exist two pointers per logical register: The first one, the in-order pointer, points to the register that represents the in-order state, the second one, the rename pointer, points to the most recent rename instance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.