Method for making three dimensional circuit integration
US5998292A · kind A · utility
480Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1997 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Nov 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method for interconnecting, through high-density micro-post wiring, multiple semiconductor wafers with lengths of about a millimeter or below. Specifically, the method of the present invention comprises etching at least one hole, defined by walls, at least partly through a semiconducting material; forming a layer of electrically insulating material to cover said walls; and forming an electrically conductive material on said walls within the channel of the hole. Microelectronic devices containing the micro-post wiring of the present invention are also disclosed herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.