Method and system for providing tapered shallow trench isolation structure profile
US5998301A · kind A · utility
48Cited by
11References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1997 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Dec 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76237
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and system for providing a shallow trench isolation structure profile on a semiconductor is disclosed. The method and system includes patterning a mask on the semiconductor substrate, etching the mask such that the mask has sloped sides, etching the semiconductor substrate to form a trench whereby the trench has tapered sides, and planarizing the semiconductor substrate to optimize the trench depth and the width of the trench opening for subsequent processes. According to the method and system disclosed herein, the present invention allows a shallow trench isolation structure profile to be formed which has tapered sides.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.