Method for making improved shallow trench isolation for semiconductor integrated circuits
US6001706A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1997 |
| Grant date | Dec 14, 1999 |
| Priority date | — |
| Expiry date | Dec 8, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method was achieved for fabricating field oxide regions (shallow trench isolation) having raised portions which are self-aligned and extend over edges of device areas. This results in FETs with improved sub-threshold characteristics and lower sub-threshold leakage currents. The method consists of forming a pad oxide and depositing a doped polysilicon layer and a hard mask layer on a silicon substrate. Shallow trenches are etched through the hard mask, doped polysilicon layer and partially into the silicon substrate. A thermal oxidation is used to form a liner oxide in the trenches and to oxidize, at a higher oxidation rate, the sidewalls of the doped polysilicon layer to form an oxide over the edges of the device areas. A gap-fill oxide is deposited in the trenches and chemical mechanical polished (CMP) back to the polysilicon layer. The remaining polysilicon layer over the device areas is selectively removed to provide a field oxide having raised portions formed over the edges of the device areas. This eliminates the wrap-around corner effect which in the prior art resulted in enhanced corner conduction and increased sub-threshold leakage currents at substrate back bias. This im…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.