Inventor · San Francisco, CA, US

Lap Chan

127Patents
28h-index
135Co-inventors
93Inventor score

Filing activity: Mar 20, 1996 → Feb 24, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US6303418A Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer Electricity 316 Expired
US6136693A Method for planarized interconnect vias using electroless plating and CMP Electricity 263 Expired
US6261935A Method of forming contact to polysilicon gate for MOS devices Electricity 194 Expired
US5856225A Creation of a self-aligned, ion implanted channel region, after source and drain formation Electricity 186 Expired
US6300177A Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials Electricity 160 Expired
US8053340B2 Method for fabricating semiconductor devices with reduced junction diffusion Electricity 97 Active
US6461900B1 Method to form a self-aligned CMOS inverter using vertical device integration Electricity 92 Expired
US6100195A Passivation of copper interconnect surfaces with a passivating metal layer Electricity 86 Expired
US6121130A Laser curing of spin-on dielectric thin films Electricity 78 Expired
US6110787A Method for fabricating a MOS device Electricity 76 Expired
US6252277A Embedded polysilicon gate MOSFET Electricity 74 Expired
US6747314B2 Method to form a self-aligned CMOS inverter using vertical device integration Electricity 72 Expired
US6252290A Method to form, and structure of, a dual damascene interconnect device Electricity 70 Expired
US5870121A Ti/titanium nitride and ti/tungsten nitride thin film resistors for thermal ink jet technology Performing Operations; Transporting 70 Expired
US6140237A Damascene process for forming coplanar top surface of copper connector isolated by barrier layers in an insulating layer Electricity 66 Expired
US6348385B1 Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant Electricity 65 Expired
US6001706A Method for making improved shallow trench isolation for semiconductor integrated circuits Electricity 62 Expired
US6495200B1 Method to deposit a seeding layer for electroless copper plating Electricity 51 Expired
US6468906B1 Passivation of copper interconnect surfaces with a passivating metal layer Electricity 45 Expired
US6313008A Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon Electricity 45 Expired
US5858870A Methods for gap fill and planarization of intermetal dielectrics Electricity 43 Expired
US6268276A Area array air gap structure for intermetal dielectric application Electricity 39 Expired
US6403485B1 Method to form a low parasitic capacitance pseudo-SOI CMOS device Electricity 38 Expired
US6387747B1 Method to fabricate RF inductors with minimum area Electricity 35 Expired
US6221727A Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology Electricity 34 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.