Trench edge spacer formation
US6005279A · kind A · utility
22Cited by
6References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 18, 1997 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Dec 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An insulating trench isolation structure is formed in a semiconductor substrate with a spacer overlying the trench edge to prevent oxide loss during subsequent etching, thereby preventing junction leakage, particulary upon silicidation. Embodiments include providing a step in the trench fill and forming the nitride spacer during gate electrode sidewall spacer formation. The protective nitride spacer etches more slowly than oxide and, hence, remains after subsequent oxide etching and cleaning.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.