Inventor · San Francisco, CA, US

Scott Luning

98Patents
22h-index
82Co-inventors
91Inventor score

Filing activity: Nov 29, 1994 → Mar 5, 2018

Most-cited inventions

PatentTitleAreaCited byStatus
US6972478B1 Integrated circuit and method for its manufacture Electricity 575 Expired
US6351013B1 Low-K sub spacer pocket formation for gate capacitance reduction Emerging Cross-Sectional Technologies 231 Expired
US5989963A Method for obtaining a steep retrograde channel profile Electricity 136 Expired
US5614765A Self aligned via dual damascene Electricity 125 Expired
US5705430A Dual damascene with a sacrificial via fill Electricity 113 Expired
US5795823A Self aligned via dual damascene Electricity 79 Expired
US7138320B2 Advanced technique for forming a transistor having raised drain and source regions Electricity 69 Expired
US5686354A Dual damascene with a protective mask for via etching Electricity 63 Expired
US6482726B1 Control trimming of hard mask for sub-100 nanometer transistor gate Electricity 57 Expired
US5691238A Subtractive dual damascene Electricity 57 Expired
US6506642B1 Removable spacer technique Electricity 37 Expired
US5770519A Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device Electricity 35 Expired
US6107149A CMOS semiconductor device comprising graded junctions with reduced junction capacitance Emerging Cross-Sectional Technologies 31 Expired
US5888867A Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration Electricity 30 Expired
US6051473A Fabrication of raised source-drain transistor devices Electricity 30 Expired
US5998272A Silicidation and deep source-drain formation prior to source-drain extension formation Electricity 26 Expired
US5482881A Method of making flash EEPROM memory with reduced column leakage current Electricity 26 Expired
US5650343A Self-aligned implant energy modulation for shallow source drain extension formation Electricity 25 Expired
US6180468A Very low thermal budget channel implant process for semiconductors Electricity 23 Expired
US6589847B1 Tilted counter-doped implant to sharpen halo profile Electricity 22 Expired
US6372587B1 Angled halo implant tailoring using implant mask Electricity 22 Expired
US6005279A Trench edge spacer formation Electricity 22 Expired
US7176110B2 Technique for forming transistors having raised drain and source regions with different heights Electricity 17 Expired
US8120120B2 Embedded silicon germanium source drain structure with reduced silicide encroachment and contact resistance and enhanced channel mobility Electricity 16 Active
US6232166A CMOS processing employing zero degree halo implant for P-channel transistor Electricity 16 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.