Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method
US6005401A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1997 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Apr 14, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2831
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.