Semiconductor integrated circuit and consumed power reducing method
US6005422A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 1996 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Dec 24, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit and a method for reducing the consumed power are provided. A comparator outputs bits having the same level, which correspond to each other, of a last input stored in a register and a current input that acts as an input signal. A zero counter counts the number of the bits having the same level output from the comparator. If the number of the bits having the same level is smaller than a predetermined number, the current input is not similar to the last input. Consequently, an instruction is given to a flip-flop to invert the current input. The inverted current input becomes similar to the last input. Thus, the consumed power of a logic can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.