Process for formation of isolation trenches with high-K gate dielectrics
US6008095A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1998 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Aug 7, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for formation of isolation trenches with high-k gate dielectrics. In an example embodiment, the process comprises depositing a high permittivity layer on the substrate. An isolation trench extending from the high permittivity layer into the substrate is etched at a selected location on the substrate. The high permittivity layer is then etched to a selected thickness, and gate electrodes are formed adjacent the trench on the high permittivity layer of the selected thickness. In another embodiment, the isolation trench is formed with an oxide liner using an NO anneal, and the high-K gate dielectric layer is optionally reduced in thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.