Erase verify scheme for NAND flash
US6009014A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1998 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Jun 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of verifying that all flash EEPROM transistors in a NAND string are properly erased without overerasing by applying a bias voltage to the source of the bottom select gate of the NAND array and applying a non-negative erase verify voltage to the control gates of each transistor during an erase verify. The bias voltage is at least equal to the erased threshold voltage of the worst case transistor to ensure proper erase verification. If all transistors are not erased, then another erase operation is performed. Erasing is repeated until the erase verify operation indicates that all transistors are properly erased. By erasing and verifying according to the present invention, the NAND array is completely and properly erased while minimizing overerasing the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.