Method and circuit for trimming the internal timing conditions of a semiconductor memory device
US6009041A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1998 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Feb 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit to trim the internal timing conditions for a semiconductor memory device including a memory matrix and circuit portions for allowing reading of the data stored in the memory matrix wherein such circuit portions include an ATD generator detecting each transition of a plurality of address terminals of the memory device to produce an ATD synchronization signal, a sense amplifier which receives an equalization a signal EQU from a generator activated by the ATD signal, and output buffers enabled by an OUTLATCH signal produced by a generator receiving the ATD signal and the EQU signal. The length of the signals is automatically trimmed according to a corresponding length code contained in a portion of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.