Programmable logic device with multi-port memory
US6011744A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 16, 1997 |
| Grant date | Jan 4, 2000 |
| Priority date | — |
| Expiry date | Jul 16, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/177
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.