Method and apparatus for improving engineering change order placement in integrated circuit designs
US6014506A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 1996 |
| Grant date | Jan 11, 2000 |
| Priority date | — |
| Expiry date | Mar 21, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool includes the steps of: (A) placing cells specified by the netlist in a layout area in a placement step, the cells including pins that are interconnected by nets; (B) verifying timing constraints in a timing verification step of the placed cells in the layout area; and (C) if the timing verification step indicates that timing does not verify in that the timing constraints are not met: (a) modifying the netlist pursuant to an engineering change order (ECO); and (b) making an ECO placement of at least one cell into the layout area by (i) picking an unplaced cell from a set of unplaced cells to be a picked cell; (ii) determining a target window within said layout area for the placement of said picked cell; (iii) mapping said picked cell inside said target window; (iv) removing said picked cell from said set of unplaced cells; (v) optimizing the placement of said picked cell by analyzing said picked cell within said target window with respect to other cells, and modifying said placement of said picked cell if it improves timing; and (vi) repeating steps (i)-(v) until said se…
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