Method for semiconductor fabrication
US6015745A · kind A · utility
5Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 18, 1998 |
| Grant date | Jan 18, 2000 |
| Priority date | — |
| Expiry date | May 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7624
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An SOI semiconductor design methodology enables the implementation of simplified STI processes by the design and formation of a shallow trench isolation frame around an electrically active semiconductor region. The simplified STI processes include the fabrication of a trench by phase edge etching, trench sidewall oxidation, TEOS fill, and, finally a chemical or mechanical polish. The attribute which enables the simple process is that all isolation images can be current minimum or near minimum size, specifically no wider than twice the over-lay tolerance of the technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.