MOS memory point
US6018475A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1998 |
| Grant date | Jan 25, 2000 |
| Priority date | — |
| Expiry date | Oct 15, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to the use of a conventional MOS transistor as a memory point in which, during programming, the well of the MOS transistor is connected to a reference potential, the drain and the source are connected to a current source adapted to bias the drain and source junctions in reverse and in avalanche so that the space charge region extends along the entire channel length, the gate is set to the reference potential if the memory point does not have to be programmed and to a distinct potential if the memory point has to be programmed; and during the reading, circuitry is provided to detect a high or low impedance state between the gate and the well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.