Method of manufacturing a thin film transistor with reduced parasitic capacitance and reduced feed-through voltage
US6020223A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 1997 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Oct 29, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of producing an improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser-assisted doping technique is applied to fabricate such transistors. A radiation filter is employed, which is transparent to light at the photolithography wavelength, but reflective or opaque at the laser wavelength. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.