Stacked semiconductor package and method of fabrication
US6020629A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1998 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Jun 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and a method for fabricating the package are provided. The package includes multiple substrates in a stacked configuration, each having a semiconductor die mounted thereon. Each substrate includes matching patterns of external contacts and contact pads formed on opposing sides of the substrate, and interconnected by interlevel conductors through the substrate. In the package, the external contacts on a first substrate are bonded to the contact pads on an adjacent second substrate, so that all of the dice in the package are interconnected. The fabrication process includes forming multiple substrates on a panel, mounting the dice to the substrates, stacking and bonding the panels to one another, and then separating the substrates from the stacked panels to form the packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.