I/O buffer circuit with pin multiplexing
US6020760A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 16, 1997 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Jul 16, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17744
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a FPGA core. Each input/output buffer circuit allows at least two signals to be time-multiplexed onto an input/output pin thereby doubling the effective input/output capacity. The input/output buffer circuits may be used to time-multiplex at least two signals onto an input pin, at least two signals onto an output pin, or both. Each input/output buffer circuit further has shared flip flops for time-multiplexing signals. The circuitry provides two connections into the FPGA core which can be used to time-multiplex at least two independent inputs or outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.