Memory system having flexible bus structure and method
US6021459A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 1997 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Apr 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0661
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system having a memory controller connected to multiple memory devices by way of a system bus. The memory controller issues device select, memory program and memory read instructions for the memory devices over the system bus, with the device select instructions including a device select address and a device select command. The memory devices each include an array of memory cells and a memory operation manager which functions to carry out memory read and program operations on the array. The memory operation manager includes an address comparator which compares the device select address received on the system bus with a local address stored in the memory device and a command decoder which detects commands on the system bus, with the memory operation manager operating to switch the memory device from a device-disabled state to a device-enabled state when the memory device receive a select address which matches the local address together with one of the device select commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.