Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching
US6021485A · kind A · utility
84Cited by
5References
24Claims
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Key dates
| Filing date | Apr 10, 1997 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Apr 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a superscalar processor implementing out-of-order dispatching and execution of load and store instructions, when a store instruction has already been translated, the load address range of a load instruction is contained within the address range of the store instruction, and the data associated with the store instruction is available, then the data associated with the store instruction is forwarded to the load instruction so that the load instruction may continue execution without having to be stalled or flushed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.