Data processing system having memory sub-array redundancy and method therefor
US6021512A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 1996 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Nov 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One or more redundant sub-arrays (324) are added to a memory (316-322) of a data processing system (300) to allow a manufacturer to compensate for defects introduced during the fabrication phase of a semiconductor device upon which it is implemented. Each of these redundant sub-arrays includes a separate and independent wordline decoder (202), bitline decoder (206), and input/output circuit (208). Furthermore, the memory to which the redundant sub-array is added is typically an on-chip memory which is organized into bit-slice sub-arrays. The bit-slice organization of the memory allows the redundant sub-array to be chained together with the on-chip memory. Data-in/data-out multiplexers are used to steer bit-slices of the data around the defective sub-arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.