Method for manufacturing a capacitor for a semiconductor arrangement

US6022786A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Martin Franosch · Munich, DE
• Wolfgang Hoenlein · Unterhaching, DE
• Helmut Klose · Munich, DE
• Gerrit Lange · Denzlingen, DE
• Volker Lehmann · Hersbruck, DE
• Hans Reisinger · Grünwald, DE
• Herbert Schaefer · Herdorf, DE
• Reinhard Stengl · Stadtbergen, DE
• Hermann Wendt · Grasbrunn, DE
• Dietrich Widmann · Unterhaching, DE

Key dates

• Filing date: Feb 27, 1998
• Grant date: Feb 8, 2000
• Expiry date: Feb 27, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/038

Abstract

For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).