Silicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devices
US6025267A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 1998 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Jul 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32134
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming self-aligned, metal silicide, (salicide), layers, on polysilicon gate structures, and on source/drain regions, located in a first region of a semiconductor substrate, while avoiding the salicide formation, on polysilicon gate structures, and on source/drain regions, located in a second region of a semiconductor substrate, has been developed. A composite insulator shape, comprising an overlying silicon nitride layer, and an underlying TEOS deposited, silicon oxide layer, is used to block polysilicon, as well as silicon regions, in the second region of the semiconductor substrate, from salicide formation. Unwanted silicon oxide spacers, created on the sides of polysilicon gate structures, during the patterning of the composite insulator shape, is selectively removed using dilute hydrofluoric acid solutions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.