Inventor · Singapore, SG

Yong Meng Lee

43Patents
11h-index
91Co-inventors
78Inventor score

Filing activity: Jul 15, 1998 → Mar 4, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US6025267A Silicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devices Electricity 91 Expired
US6372569B1 Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performance Electricity 25 Expired
US7193254B2 Structure and method of applying stresses to PFET and NFET transistor channels for improved performance Electricity 25 Expired
US6511884B1 Method to form and/or isolate vertical transistors Electricity 22 Expired
US6927104B2 Method of forming double-gated silicon-on-insulator (SOI) transistors with corner rounding Electricity 19 Expired
US6835609B1 Method of forming double-gate semiconductor-on-insulator (SOI) transistors Electricity 16 Expired
US9524911B1 Method for creating self-aligned SDB for minimum gate-junction pitch and epitaxy formation in a fin-type IC device Electricity 15 Active
US7737009B2 Method of implanting a non-dopant atom into a semiconductor device Electricity 12 Active
US7256084B2 Composite stress spacer Electricity 12 Expired
US6258648A Selective salicide process by reformation of silicon nitride sidewall spacers Electricity 11 Expired
US7445978B2 Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS Electricity 11 Expired
US6107140A Method of patterning gate electrode conductor with ultra-thin gate oxide Electricity 9 Expired
US7893502B2 Threshold voltage improvement employing fluorine implantation and adjustment oxide layer Electricity 8 Active
US6583011B1 Method for forming damascene dual gate for improved oxide uniformity and control Emerging Cross-Sectional Technologies 8 Expired
US7309637B2 Method to enhance device performance with selective stress relief Electricity 7 Expired
US6787404B1 Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitance Electricity 6 Expired
US7141854B2 Double-gated silicon-on-insulator (SOI) transistors with corner rounding Electricity 5 Expired
US8624329B2 Spacer-less low-K dielectric processes Electricity 5 Active
US7442611B2 Method of applying stresses to PFET and NFET transistor channels for improved performance Electricity 4 Active
US7393746B2 Post-silicide spacer removal Electricity 4 Active
US9385030B2 Spacer to prevent source-drain contact encroachment Electricity 4 Active
US8716081B2 Capacitor top plate over source/drain to form a 1T memory device Electricity 4 Active
US6436754B1 Selective salicide process by reformation of silicon nitride sidewall spacers Electricity 3 Expired
US7977185B2 Method and apparatus for post silicide spacer removal Electricity 3 Expired
US8274115B2 Hybrid orientation substrate with stress layer Electricity 3 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.